The NAND gate is a popular logic element because it can be used as a
universal gate; that is, NAND gates can be used in combination to perform
the AND, OR, and inverter operations. The universal property of the NAND
gate will be examined thoroughly.
The term NAND is a contraction of NOT-AND and implies an AND function with a
complemented (inverted) output. The standard logic symbol for a 2-input NAND
gate and its equivalency to an AND gate followed by an inverter are shown in
Figure 1(a), where the symbol ≡ means equivalent to. A rectangular outline
symbol is shown in part (b).
FIGURE 1: Standard NAND gate logic symbols (ANSI/IEEE Std. 91-1984/Std. 91a-1991) |
Operation of a NAND Gate
A NAND gate produces a LOW output only when all the inputs are HIGH. When any of the inputs is LOW, the output will be HIGH. For the specific case of a 2-input NAND gate, as shown in Figure 1 with the inputs labeled A and B and the output labeled X, the operation can be stated as follows:For a 2-input NAND gate, output X is LOW only when inputs A and B are HIGH; X is HIGH when either A or B is LOW, or when both A and B are LOW.
This operation is opposite that of the AND in terms of the output level. In a NAND gate, the LOW level (0) is the active or asserted output level, as indicated by the bubble on the output. Figure 2 illustrates the operation of a 2-input NAND gate for all four input combinations, and Table 3–7 is the truth table summarizing the logical operation of the 2-input NAND gate.
FIGURE 2: Operation of a 2-input NAND gate. Open file F03-27 to verify NAND gate operation. |
NAND Gate Operation with Waveform Inputs
Now let’s look at the pulse waveform operation of a NAND gate. Remember
from the truth table that the only time a LOW output occurs is when all of
the inputs are HIGH.
EXAMPLE 1
If the two waveforms A and B shown in Figure are applied to the NAND gate
inputs, determine the resulting output waveform.
Solution
Output waveform X is LOW only during the four time intervals when both
input waveforms A and B are HIGH as shown in the timing diagram.
EXAMPLE 2
Show the output waveform for the 3-input NAND gate in Figure with its
proper time relationship to the inputs.
Solution
The output waveform X is LOW only when all three input waveforms are HIGH
as shown in the timing diagram.
Inherent in a NAND gate’s operation is the fact that one or more LOW inputs
produce a HIGH output. Table 3–7 shows that output X is HIGH (1) when any of
the inputs, A and B, is LOW (0). From this viewpoint, a NAND gate can be
used for an OR operation that requires one or more LOW inputs to produce a
HIGH output. This aspect of NAND operation is referred to as negative-OR.
The term negative in this context means that the inputs are defined to be in
the active or asserted state when LOW.
For a 2-input NAND gate performing a negative-OR operation, output X is HIGH
when either input A or input B is LOW, or when both A and B are LOW.
EXAMPLE 3
For the 4-input NAND gate in Figure, operating as a negative-OR gate,
determine the output with respect to the inputs.
Solution
The output waveform X is HIGH any time an input waveform is LOW as shown
in the timing diagram.
Logic Expressions for a NAND Gate
The Boolean expression for the output of a 2-input NAND gate is:
Once an expression is determined for a given logic function, that function can be evaluated for all possible values of the variables. The evaluation tells you exactly what the output of the logic circuit is for each of the input conditions, and it therefore gives you a complete description of the circuit’s logic operation. The NAND expression can be extended to more than two input variables by including additional letters to represent the other variables.
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