NAND Logic

As you have learned, a NAND gate can function as either a NAND or a negative-OR because, by DeMorgan’s theorem,

Consider the NAND logic in Figure 5–20. The output expression is developed in the following steps:
FIGURE 1: NAND logic for X 5 AB 1 CD.

As you can see in Figure 2, the output expression, AB 1 CD, is in the form of two AND terms ORed together. This shows that gates G2 and G3 act as AND gates and that gate G1 acts as an OR gate, as illustrated in Figure 2(a). This circuit is redrawn in part (b) with NAND symbols for gates G2 and G3 and a negative-OR symbol for gate G1. Notice in Figure 2(b) the bubble-to-bubble connections between the outputs of gates G2 and G3 and the inputs of gate G1.
Figure 2
Figure 2(a) Original NAND logic diagram showing effective gate operation relative to the output expression

Figure 2(b) Equivalent NAND/Negative-OR logic diagram


Figure 2(c) AND-OR equivalent


Since a bubble represents an inversion, two connected bubbles represent a double inversion and therefore cancel each other. This inversion cancellation can be seen in the previous development of the output expression AB + CD and is indicated by the absence of barred terms in the output expression. Thus, the circuit in Figure 2(b) is effectively an AND-OR circuit, as shown in Figure 2(c).

NAND Logic Diagrams Using Dual Symbols

All logic diagrams using NAND gates should be drawn with each gate represented by either a NAND symbol or the equivalent negative-OR symbol to reflect the operation of the gate within the logic circuit. The NAND symbol and the negative-OR symbol are called dual symbols. When drawing a NAND logic diagram, always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-tobubble or nonbubble-to-nonbubble. In general, a bubble output should not be connected to a non-bubble input or vice versa in a logic diagram.
Figure 3 shows an arrangement of gates to illustrate the procedure of using the appropriate dual symbols for a NAND circuit with several gate levels. Although using all
NAND symbols as in Figure 3(a) is correct, the diagram in Figure 3(b) is much easier to “read” and is the preferred method. As shown in Figure 3(b), the output gate is represented with a negative-OR symbol. Then the NAND symbol is used for the level of gates right before the output gate and the symbols for successive levels of gates are alternated as you move away from the output.
Figure 3(a) Several Boolean steps are required to arrive at final output expression

Figure 3(b) Output expression can be obtained directly from the function of each gate symbol in the diagram


The shape of the gate indicates the way its inputs will appear in the output expression and thus shows how the gate functions within the logic circuit. For a NAND symbol, the inputs appear ANDed in the output expression; and for a negative-OR symbol, the inputs appear ORed in the output expression, as Figure 3(b) illustrates. The dual-symbol diagram in part (b) makes it easier to determine the output expression directly from the logic diagram because each gate symbol indicates the relationship of its input variables as they appear in the output expression.
EXAMPLE 1 
Redraw the logic diagram and develop the output expression for the circuit in Figure using the appropriate dual symbols
Solution

Redraw the logic diagram in Figure  with the use of equivalent negative-OR symbols as shown in Figure : 

 Writing the expression for X directly from the indicated logic operation of each gate gives :